The present invention relates to input stages for electronic circuits, and in particular to an input buffer circuit that provides selected different input impedances while maintaining the same output properties.
Input buffer circuits are commonly used to isolate a load from a source, for example when driving an signal from an integrated circuit (IC) into a load. The load may comprise another integrated circuit, and normally it is desirable that the buffer circuit have selected input and output impedances. This conventionally is accomplished by specially designing the buffer to have the selected impedances.
An input buffer may be used at an input to an integrated circuit (IC), such as an application specific integrated circuit (ASIC). The ASIC is then a load and an analog signal from an IC source is driven through the buffer into the ASIC. The buffer may be designed to have output impedance as required by an ASIC with which it is to be used. If the ASIC always serves as a load for a particular type of IC source, then the buffer may also be designed to have selected input impedance, usually xe2x80x9clowxe2x80x9d or xe2x80x9chighxe2x80x9d input impedance, depending upon the nature of the driver. However, if the ASIC is used with various types of driver circuits and the nature of the driver circuit with which it will be used is not known beforehand, then the buffer usually is designed to have input impedance in accordance with an industry standard. In this case, it may and often does turn out that the industry standard input impedance is not best for connection of the ASIC to any particular driver circuit. In the wireless telephone industry, for example, a buffer may be at an input to an ASIC comprising a phase-locked loop (PLL) receiver circuit, which type of ASIC is driven by various types of sources. Since the nature of a driver circuit to which a buffer will connect a PLL receiver is usually not known ahead of time, a buffer for a PLL receiver is designed to have either low or high input impedance in accordance with an industry standard. For an ASIC comprising a PLL receiver, the industry standard is for an input buffer to have high input impedance, but the industry standard input impedance is often not the best choice for the buffer circuit. For example, if a transceiver drives a radio frequency (RF) signal to the PLL receiver through a buffer circuit, high buffer input impedance does not enhance a desired objective of providing a current efficient and parasitic insensitive way of implementing the RF interface. For this application, the better solution would be to have low buffer input impedance, which as compared with high buffer input impedance would improve current efficiency and insensitivity to parasitics and generally obviate the need for external components such as pull-up resistors.
It would therefore be desirable to provide a buffer circuit for use at an input to an ASIC, the input impedance to which buffer can selectively be controlled to accommodate efficiently connecting the ASIC to various types of driver circuits, while maintaining uniform output properties from the buffer.
In accordance with the present invention, there is provided a multi-impedance input buffer circuit for driving an analog signal from a source to a load. The buffer circuit includes at least one amplifier circuit having an input for receiving the analog signal from the source and an output for delivering the analog signal to the load. The at least one amplifier is responsive to a first control signal to have low input impedance while coupling the analog signal from the source to the load and is responsive to a second control signal to have high input impedance while coupling the analog signal from the source to the load.
The at least one buffer circuit amplifier may comprise first and second amplifier circuits for delivering the analog signal from the source to the load. The first amplifier circuit has an input for receiving the analog signal from the source, an output for delivering the analog signal to the load, and an impedance control. The first amplifier is responsive to application of the first control signal at its impedance control to be enabled to couple the analog signal from the source to the load and to have low input impedance, and is responsive to absence of the first control signal at its impedance control to be disabled from coupling the analog signal from the source to the load and to have high input impedance. The second amplifier circuit has an input connected to the first amplifier circuit input for receiving the analog signal from the source, an output connected to the first amplifier circuit output for delivering the analog signal to the load, and an impedance control. The second amplifier circuit is responsive to application of a second control signal at its impedance control to be enabled to couple the analog signal from the source to the load and to have high input impedance, and is responsive to absence of the first control signal at its impedance control to be disabled from coupling the analog signal from the source to the load and to have high impedance at its input.
The invention also contemplates a method of operating a buffer circuit for driving an analog signal from a source to a load. The method comprises the steps of coupling the analog signal from the source to an input to the buffer circuit; connecting the output from the buffer circuit to the load; and controlling the buffer circuit to have either low input impedance and determined output impedance or high input impedance and selected output impedance.
The foregoing and other advantages and features of the invention will become apparent upon a consideration of the following detailed description, when taken in conjunction with the accompanying drawings.